In the field of e.g. embedded non-volatile memory modules, the optimization of the memory cell size is important. Furthermore, for standalone memories, CMOS (Complementary Metal Oxide Semiconductor) process complexity should be taken into account. Thus, the tradeoff between process complexity adder and chip area savings may become more important in embedded non-volatile memory modules compared to standalone memories.
In general, area optimization of e.g. a non-volatile memory cell becomes more and more important. By way of example, a so-called Uniform Channel Program (UCP) memory cell (e.g. a memory cell which is programmed and erased using the so-called Fowler-Nordheim tunneling mechanism) is a type of memory cell, the footprint of which is desired to be optimized. In a conventional layout, in a UCP memory cell arrangement, the metal pitch is limited due to interference effects (in general, due to design rules). This limitation may affect the shrink path of a UCP memory cell arrangement, in general, of a memory cell arrangement.
In a conventional memory cell arrangement, local bit lines and global bit lines are used to minimize disturbs for write operation and read operation, hence area optimization is limited.